The debug, trace, and test tool UDEÆ Universal Debug Engine 2026, presented by PLS Programmierbare Logik & Systeme at embedded world 2026 in Nuremberg in Hall 4, booth 4-310, now enables debugging, runtime monitoring, and validation of special, data flow-oriented algorithms, such as those currently incorporated into embedded AI applications. As part of a research project funded by the German Federal Ministry for Economic Affairs and Energy, PLS developed innovative tools for the Bosch Data Flow Architecture (DFA) and integrated them into UDE 2026.
The Bosch DFA is a highly parallel, dynamically configurable hardware accelerator that enables very highperformance data flow-oriented calculations, which are essential for AI applications. Due to its small chip area usage and low power consumption, DFA is perfectly suited for integration into embedded systems or systems-on-chips (SoCs).
Unlike conventional processor architectures, where algorithms are primarily executed via sequences of machine instructions, the Bosch DFA implements the respective task by combining mathematical baseblocks, forming a native data flow graph. This ensures significantly higher efficiency. However, as such a graph cannot be debugged with conventional debugger functions, PLS has expanded its UDE to incorporate a variety of new special features for analysis and debugging DFA's data flow graph.
As a peripheral module of an embedded system or SoC, DFA can be started and stopped individually or synchronously together with the main cores of the host controller. It is integrated into the debugger’s user interface as an additional core and is a member of a run control group that controls the debug synchronization of the cores. This allows both, parallel debugging of the main cores' application and simultaneous observation of the DFA accelerator. Single-stepping enables detailed examination of the data flow.
This allows the configuration of the individual mathematical base-blocks to be checked and modified in the targeted manner. The data flow graph is visualized by means of a graphical representation of the interconnections of the base-blocks for a specific algorithm as a tree or block diagram. In addition to different display formats that can be individually adapted to the needs of the respective developer, an export and import function for DFA configurations has also been implemented.
Using a SystemC simulation model, the runtime data of the DFA can be recorded. This data can be displayed as decoded text and as a time-correlated graphical representation by an additional software component that was also developed as part of the research project.
The additional functions for testing and runtime analysis of DFA algorithms integrated into UDE 2026 are now available for first automotive microcontrollers from various semiconductor manufacturers implementing DFA as well as for virtual prototyping on the DFA simulation model.
The Bosch DFA is a highly parallel, dynamically configurable hardware accelerator that enables very highperformance data flow-oriented calculations, which are essential for AI applications. Due to its small chip area usage and low power consumption, DFA is perfectly suited for integration into embedded systems or systems-on-chips (SoCs).
Unlike conventional processor architectures, where algorithms are primarily executed via sequences of machine instructions, the Bosch DFA implements the respective task by combining mathematical baseblocks, forming a native data flow graph. This ensures significantly higher efficiency. However, as such a graph cannot be debugged with conventional debugger functions, PLS has expanded its UDE to incorporate a variety of new special features for analysis and debugging DFA's data flow graph.
As a peripheral module of an embedded system or SoC, DFA can be started and stopped individually or synchronously together with the main cores of the host controller. It is integrated into the debugger’s user interface as an additional core and is a member of a run control group that controls the debug synchronization of the cores. This allows both, parallel debugging of the main cores' application and simultaneous observation of the DFA accelerator. Single-stepping enables detailed examination of the data flow.
This allows the configuration of the individual mathematical base-blocks to be checked and modified in the targeted manner. The data flow graph is visualized by means of a graphical representation of the interconnections of the base-blocks for a specific algorithm as a tree or block diagram. In addition to different display formats that can be individually adapted to the needs of the respective developer, an export and import function for DFA configurations has also been implemented.
Using a SystemC simulation model, the runtime data of the DFA can be recorded. This data can be displayed as decoded text and as a time-correlated graphical representation by an additional software component that was also developed as part of the research project.
The additional functions for testing and runtime analysis of DFA algorithms integrated into UDE 2026 are now available for first automotive microcontrollers from various semiconductor manufacturers implementing DFA as well as for virtual prototyping on the DFA simulation model.
