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ynopsys Announces the Tapeout of NEC Electronics' Latest EMMA System LSI Using IC Compiler
Successful Tapeout of Large 7-Million-Instances Design was Critical in Meeting NEC Electronics' Time-to-Market Requirements(PresseBox) ( Mountain View CA, )
"The EMMA series of chips from NEC Electronics is a core technology for the digital A/V product line," said Masao Hirasawa, General Manager, Digital Consumer LSI Division at NEC Electronics. "EMMA is used by many leading digital consumer companies, so meeting time-to-market targets is critical. IC Compiler along with Synopsys Professional Services enables a predictable flow that requires less iteration for a successful tapeout. That is why we have chosen IC Compiler for this important NEC Electronics project."
IC Compiler's comprehensive place and route capabilities are designed to enable customers like NEC Electronics to leverage predictable results with less iteration to meet aggressive delivery schedules. The 90 nanometer EMMA design consists of more than 7 million instances with several hundred macros running at multiple speeds. The size of the flat design combined with the time constraints put a high demand on NEC Electronics and Synopsys Professional Services to deliver a solution to customers with highest quality of results.
"IC Compiler continues to meet the demands of our customers as design challenges continue to increase," said Dr. Chi-Foon Chan, President and Chief Operating Officer, Synopsys. "The EMMA chip series from NEC Electronics employs leading-edge technologies that require leading-edge place-and-route solutions to deliver predictable, high quality of results."
About IC Compiler
IC Compiler provides hand-craft-quality macro placement, intelligent power network support, and MinChip technology for automatic die-size reduction, all on a single timer foundation that enables faster time to closure with higher quality of results (QoR). For complex designs, a concurrent flow that seamlessly blends planning and implementation tasks and offers an integrated environment with a single timer and high correlation with sign-off is critical. Concurrent planning and implementation replaces the traditional "plan-then-implement" methodology, resulting in faster time to tapeout and reduced design cost.
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