Synopsys Galaxy Implementation Platform enables first-pass silicon success on Infineon's 40-nanometer X-GOLD 626 wireless product

IC Compiler capabilities for low power, hierarchical design and multi-corner/multi-mode optimisation enable tapeout ahead of schedule

(PresseBox) ( Mountain View CA, )
Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that the Galaxy(TM) Implementation Platform has helped Infineon Technologies AG (NYSE: IFX) achieve firstpass silicon success of the 40nanometer (nm) baseband processor for its X-GOLD(TM) 626 3G wireless analog and digital systeminpackage (SIP). Infineon utilised the Galaxy platform's powerful implementation flow to optimise the chip's multiple functional modes with multicorner/multimode (MCMM) technology, taking advantage of the links between Synopsys' Design Compiler® RTL synthesis solution and IC Compiler placement and routing. The Galaxy platform's extensive support for low power and hierarchical design techniques, coupled with its signoff capabilities, was essential to achieve Infineon's tight schedule and highperformance, low power and area goals. As a result, Infineon met its design targets and taped out the baseband processor for the X-GOLD 626 wireless product ahead of schedule.

"One of the key challenges we had in designing the X-GOLD 626 baseband processor was optimising the design for highest performance and lowest power, without compromising on robustness and quality," said Hartmut Hiller, vice president of Design Methodology and Implementation at Infineon Technologies. "Synopsys' Galaxy platform includes essential advanced low power capabilities which, along with its strength in hierarchical design and concurrent MCMM optimisation, were critical to our firstpass silicon success. Synopsys' excellent global support and the Galaxy platform's robust implementation and signoff technologies, we successfully taped out the chip ahead of schedule."

Infineon's X-GOLD 626 is a complex multimilliongate analog and digital SIP that integrates a power management unit to enable bestinclass power consumption in both active and idle modes. Infineon's design team captured the chip's complex power architecture with the IEEE 1801 (UPF) standard. Power management features implemented using the Galaxy platform included voltage islands with MTCMOS power gating and multithreshold libraries. In addition, by implementing a hierarchical design flow and support for multiple internal clocks, the Galaxy platform delivered outstanding quality of results, meeting Infineon's highperformance, low power and area goals.

"Our customers are facing several challenges: to produce the highestquality products within the shortest amount of time and with bestinclass performance, power and area," said Dr. Antun Domic, senior vice president and general manager, Implementation Group at Synopsys. "Infineon's decision to deploy our Galaxy Implementation Platform, including IC Compiler, for their advanced wireless designs will enable them to continue to aggressively focus on bringing differentiated wireless SoC solutions to market."
Für die oben stehenden Pressemitteilungen, das angezeigte Event bzw. das Stellenangebot sowie für das angezeigte Bild- und Tonmaterial ist allein der jeweils angegebene Herausgeber (siehe Firmeninfo bei Klick auf Bild/Meldungstitel oder Firmeninfo rechte Spalte) verantwortlich. Dieser ist in der Regel auch Urheber der Pressetexte sowie der angehängten Bild-, Ton- und Informationsmaterialien.
Die Nutzung von hier veröffentlichten Informationen zur Eigeninformation und redaktionellen Weiterverarbeitung ist in der Regel kostenfrei. Bitte klären Sie vor einer Weiterverwendung urheberrechtliche Fragen mit dem angegebenen Herausgeber. Bei Veröffentlichung senden Sie bitte ein Belegexemplar an