Synopsys Galaxy Implementation Platform Used by TSMC for 28nm Process
Product Qualification Vehicle Test Chip Tapeout Includes Advanced Routing Rules, Low Power and Signoff Capabilities
TSMC's complex 28nm test chip design consisted of more than 200 million gates of logic and memory combining multiple IP cores and custom designed blocks. The chip's multiple power and clock domains presented additional design challenges that were efficiently handled by the Galaxy platform tools. TSMC deployed advanced methodologies during the test chip design to address hierarchical power implementation, DFT, advanced routing rules and manufacturability compliance. To address the design's multiple multivoltage blocks, TSMC utilized the Galaxy platform's hierarchical low power flow, including power intent definition described with UPF. This approach enabled the engineering team to implement different subblocks of the design concurrently, resulting in faster overall timetoresults. In addition, the Galaxy tools were used to successfully deploy TSMC's pulsed latch approach to maximize power savings across the chip. To validate 28nm manufacturing compliance, TSMC used Synopsys' IC Compiler Zroute DFMaware routing capabilities.
"We continuously work with Synopsys to identify EDA and manufacturing solutions that address the challenges of the latest advanced semiconductor processes," said ST Juang, senior director of design infrastructure marketing at TSMC. "As a result of our PQV test chip design project, we have successfully used Synopsys' Galaxy Implementation Platform in our 28nanometer process, including capabilities for hierarchical low power implementation, routing rules and manufacturing compliance. We appreciate Synopsys' ongoing collaboration during our aggressive process development and deployment projects that allow us to deploy our solutions to our common customers in a very timely manner."
"As semiconductor process technologies continue to increase in complexity it is essential for industry leaders like TSMC and Synopsys to engage at deep technical levels," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "Through the Galaxy Implementation Platform collaboration with TSMC on its advanced 28nanometer PQV test chip project, our customers can be assured that the Galaxy Platform can be used successfully in this new technology. This will enable predictable silicon success as they embark on their next design projects."
Synopsys, Inc. (Nasdaq: SNPS) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and fieldprogrammable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, systemtosilicon verification and timetoresults. These technologyleading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has more than 65 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com.
Diese Pressemitteilungen könnten Sie auch interessieren
Weitere Informationen zum Thema "Hardware":
Was sind (KI-)Akzeleratoren?
Unter Akzeleratoren versteht man „Turbo-Prozessoren“, hauptsächlich im Bereich von KI-Anwendungen, die spezifische Aufgaben wie zum Beispiel Mustererkennung, Analyse unstrukturierter Daten, Monte-Carlo-Simulationen, Streaming-Aufgaben oder den Aufbau neuronaler Netze übernehmen.Weiterlesen