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Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards in a Single PHY
New DDR multiPHY Allows One Chip to Target Multiple Applications(PresseBox) ( MOUNTAIN VIEW, Calif., USA, )
"Memory interfaces continue to be one of the key IP requirements we see in chip development. New standards such as DDR3, DDR3L and LPDDR2 are designed to meet system performance requirements while utilizing less power," said Dr. Keh-Ching Huang, Head of Marketing and IP Solution Planning at Global Unichip. "By supporting all facets of the DDR standards, Synopsys' unique DesignWare DDR multiPHY enables us to quickly incorporate the necessary functionalities into our SoC designs with less risk."
The DesignWare DDR multiPHY is architected for extremely low power consumption and features Delay Lock Loop (DLL) bypass modes for operation below 200 MHz. It also features an I/O retention mode that allows the chip's power supplies to be shut down completely while a small number of I/Os remain powered on to keep the external SDRAMs in self refresh mode. The DesignWare DDR multiPHY is designed to support the anticipated DDR3U standard operating at 1.2 or 1.25 V. Additionally, the DesignWare DDR multiPHY provides builtin data training circuits to enable insystem calibration, providing optimized systemlevel timing without material interaction with the memory controller.
The DDR multiPHY is a hard macro similar to Synopsys' complementary DDR PHY offerings. Hard DDR PHYs offer significant benefits over "soft" PHYs or all digital PHYs such as:
- Quick integration. All pieces of the PHY come from one vendor and have been verified together
- Minimal timing closure problems. Known performance, proven in silicon
- Better performance margins. Lower jitter, better duty cycle and more supply noise rejection
- Area optimized circuits. Each bit path is designed with matched flight times on the data buses
"It has become as important to minimize power as it has to minimize overall chip cost in portable electronics," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "The DesignWare DDR multiPHY not only offers designers the flexibility to utilize any DDR SDRAM in the system through simple software control, it also features a powerconscious design that minimizes the silicon area and cost."
The DesignWare DDR multiPHY is a part of Synopsys' comprehensive DesignWare DDR IP offering that consists of digital controllers and PHY IP supporting DDR, DDR2, DDR3, Mobile DDR and now LPDDR2. The comprehensive portfolio of DDR IP supports leading 130nm, 90nm, 65nm, 55nm and 45/40nm technologies. Synopsys helps lower integration risk by providing highquality DDR IP solutions that have been implemented in hundreds of applications and are shipping in volume production.
The DesignWare DDR multiPHY is available now. For more product information and video demonstrations of DesignWare DDR IP, visit: http://www.synopsys.com/ddr
IP Synopsys is a leading provider of highquality, siliconproven interface and analog IP solutions for systemonchip designs. Synopsys' broad IP portfolio delivers complete connectivity IP solutions consisting of controllers, PHY and verification IP for widely used protocols such as USB, PCI Express, DDR, SATA, Ethernet, HDMI and MIPI IP including 3G DigRF, CSI-2 and D-PHY. The analog IP family includes Analogto-Digital Converters, Digitalto-Analog Converters, Audio Codecs, Video Analog Front Ends, Touch Screen Controllers and more. In addition, Synopsys offers SystemC transactionlevel models to build virtual platforms for rapid, presilicon development of software. With a robust IP development methodology, extensive investment in quality and comprehensive technical support, Synopsys enables designers to accelerate timetomarket and reduce integration risk. For more information on DesignWare IP, visit: http://www.synopsys.com/.... Follow us on Twitter at http://twitter.com/....
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