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Cortus Releases the World's Smallest 32-bit Microcontroller IP Core
Cortus completes the delivery of its 2012 processor roadmap with the release of the APS1 / The APS1 is aimed at simpler embedded systems on chip requiring smaller code & data memories and a tiny silicon footprint
The Cortus APS1 is a native 32-bit core with a modern RISC architecture. In common with other Cortus processors, the APS1 has a 5 to 7 stage integer pipeline with out-of-order completion ensuring that most integer instructions (load and stores included) are executed in a single cycle. It is the fourth member of the Cortus microcontroller IP core family to be released in 2012 complementing the larger energy efficient APS3R, high performance APS5 and the floating point FPS6 cores.
"We are proud to break our own record in terms of 32-bit core size", said Michael Chapman, CEO and President of Cortus. He adds, "Our first product - the APS3 - pioneered the market for silicon efficient 32-bit processor cores and with the APS1 we have an even more compact core". Michael Chapman explains, "With the APS1 released, there is almost no reason to continue to use 8-bit cores. SoC developers benefit from an easier SW development cycle, more performance and lower power consumption".
The APS1 has a fully 32-bit architecture with 16 general purpose registers. Its CPU gatecount starts at about 6800 gates. In the TSMC 90 nm technology this can be as small as 0.03 mm2 (Dolphin SESAME-HD library).
The APS1 is an ideal candidate for Internet of Things (IoT) applications such as managing sensors or handling simpler wireless protocols. It is also well suited to managing I/O and for implementing programmable state machines.
Applications running on 8-bit processor cores will benefit from moving to APS1. The Cortus APS1 fully supports developing with C or C++ and does not require any coding in assembler. With more processing performed per cycle, fewer cycles are needed compared to an 8-bit core and the processor spends more time asleep. With a larger register set fewer memory accesses are required; further conserving energy. For more complex processor applications requiring more than 64 KB data and 64 KB code memory, the APS3R provides an excellent upgrade path.
As a member of the Cortus family of processors, the APS1 interfaces to all of Cortus' peripherals including the Ethernet 10/100 MAC, USB 2.0 Device and USB 2.0 OTG via the efficient APS bus. It also shares the simple vectored interrupt structure which ensures rapid, real time interrupt response, with low software overhead.
The APS toolchain and IDE (for C and C++) are available to licensees free of charge, and it can be customised and branded for final customer use. Ports of various RTOSs are available such as FreeRTOS, Micrium µC/OS.
Cortus is exhibiting at electronica 2012 in Munich, Germany from 13th-16th November in Hall A6, booth 511.
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