"The IC Compiler 2007.12 release delivers compelling core-technology improvements. We are enabling fundamentally new usage models with concurrent hierarchical design which can deliver significant productivity advantages for customers currently using a sequential process of design planning followed by implementation," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "With this foundation now in place, Synopsys is positioned very well for extending this capability to the next phase of automatic minimum-die hierarchy generation, making hierarchical design dramatically easier."
Historically, "plan-then-implement" flows have worked well for simple designs. However, for complex designs, these flows lead to late discovery of physical design issues, resulting in overdesign and often requiring iterations back to the early planning stages. For these complex designs, a concurrent flow that seamlessly blends planning and implementation tasks and offers an integrated environment with a single timer and high correlation with sign-off becomes increasingly critical. IC Compiler 2007.12 provides hand-craft-quality macro placement, intelligent power network support, and MinChip technology for automatic die-size reduction, all on a single timer foundation that enables faster time to closure with higher quality of results (QoR). This flow is differentiated by a high degree of automation combined with high-quality optimization.
Prominent among core-technology advances in the 2007.12 release are optimization improvements which maintain IC Compiler's QoR advantage while slashing total runtime by 30 percent, as validated across a broad range of 65-nanometer (nm) customer designs. IC Compiler 2007.12 introduces unique advances in clock tree synthesis, such as an innovative new clustering algorithm which delivers 20 percent reduction in clock buffering area to improve routing congestion as well as power dissipation. In addition, new skew optimization enables improved timing closure for challenging designs, and an integrated clock-gate merging capability delivers another five to ten percent reduction in clock tree power.